The invention relates to a trench transistor.
An important characteristic quantity of semiconductor components is their on resistance. A reduction of the on resistance generally entails a lowering of the fabrication costs since, with performance data remaining the same, the dimensions of the semiconductor component can be decreased.
In practice, however, it is often necessary to dispense with optimizing the on resistance since measures that oppose a lowering of the on resistance are often implemented in order to safeguard specific properties of the semiconductor components.
The problem area described above shall be explained again by way of example below with reference to FIGS. 1 to 5.
FIG. 2 shows a construction (illustrated in simplified fashion) of a trench transistor 1 in a cross-sectional illustration. The detail from this trench transistor 1 that can be seen in FIG. 2 has a first and a second trench (cell array trench) 2, into which a gate electrode 3 and a field electrode 3′ are in each case introduced, a mesa region 4 situated between the cell array trenches 2, said mesa region having an n+-doped source region 5, a p-doped body region 6 and an n-doped drift region 7, and also field oxide layers 8 and gate oxide layers 9 enclosing the gate electrode 3 and the field electrode 3′. The gate electrode 3 is generally electrically insulated (not shown here) from the field electrode 3′. Charges present in the drift zone 7 are for the most part compensated for by the field electrodes 3′. As a result of such compensation, in accordance with the dependence on the distance between the cell array trenches 2, the drift zone 7 can still be depleted despite high doping, whereby the blocking capability of the trench transistor 1 is improved.
As soon as field electrodes are provided in an additional trench in the edge region of the trench transistor 1, said additional trench being configured with the same or approximately the same depth as the cell array trenches 2, in order to block the penetration of edge leakage currents into the cell array, excessive field increases that lower the breakdown voltage are generated at the corners at which the trench bottoms meet. This problem area is illustrated in FIG. 5.
FIG. 4 shows an example of an “open” chip design in plan view. The illustration shows a plurality of trenches 2, into each of which a field electrode 3′ and field oxide layers 8 and also gate electrodes 3 and gate oxide layers 9 (which cannot be seen) are introduced. The section in FIGS. 4-11 runs along a plane which, with regard to FIGS. 2 and 3, runs perpendicular to the plane of the drawing in horizontal orientation and intersects the regions 8, 3′ and 4 (“deepened plan view”). The upper part in FIG. 5 shows a part of the edge of the chip design and the lower part in FIG. 5 shows a part of the cell array or cell array edge of the chip design. In this case, the middle trench 2 symbolizes one or a plurality of cell array trenches (that is to say that a plurality of cell array trenches may also be provided) and the trenches 2′ provided on the left and on the right of the middle cell array trench 2 symbolize edge trenches in each case. The advantage of this chip design is an avalanche breakdown distributed uniformly over the cell array of the trench transistor 1. What is disadvantageous about such a chip design is that leakage currents can penetrate unimpeded into the mesa regions 4 from the edge region of the trench transistor 1, as is indicated by the arrows denoted by reference numeral 12. A further disadvantage is that a dedicated mask is required for fabricating the body region in the edge region of the chip design.
As is shown in FIG. 5, such leakage currents can be avoided by means of an additional transverse trench 13, which runs perpendicular to the rest of the trenches 2, 2′ and the field electrode 3″ of which is connected to the end sides of the field electrodes 3′ of the trenches 2, 2′. What is disadvantageous in this case, however, in turn is that lower breakdown voltages occur in the edge region, that is to say at the interface between the trenches 2, 2′ and the transverse trench 13, and so the avalanche breakdown occurs at lower voltages in this region, which is symbolized by the arrows denoted by reference numeral 14: a breakdown voltage that is approximately 30% lower than within the cell array occurs at the ends (end sides) of the mesa regions 4.
The lowering of the breakdown voltage that is brought about by the transverse trench can be compensated for, as already mentioned, by the provision of reserves in the breakdown voltage, e.g. through larger epitaxial thickness and trench depth. The breakdown (“avalanche breakdown”) is nevertheless effected locally, for example in the region of the transverse trench of the trench transistor in FIG. 5. A large part of the energy of the avalanche breakdown pulse would thus also be dissipated in this areally limited edge volume, which, without further cost-intensive countermeasures, would lead to premature destruction of the trench transistor. Moreover, the provision of such reserves entails an increase in the on resistance. The introduction of a transverse trench 13, as shown in FIG. 5, has a similar effect to decreasing the mesa width, on account of the additional charge depletion brought about by the field plates, and leads to the lowering of the breakdown voltage.
FIG. 1 shows the breakdown voltage of a trench transistor having a small trench spacing as a function of the width of the mesa regions (semiconductor regions between the cell array trenches). FIG. 1 clearly shows that, in the case of trench transistors having a small trench spacing (“dense trench regime”), the breakdown voltage rises as the trench spacing increases, that is to say as the width of the mesa regions increases. Conventional trench transistors having a significantly larger trench spacing exhibit the opposite behavior.
When high voltages are present, in the case of trench transistors having a small trench spacing, the avalanche breakdown takes place in the region of the bottoms of the trenches 2, 2′, as is symbolized by the arrow denoted by reference numeral 10 in FIG. 2. In contrast to this, as is shown in FIG. 3, in the case of a trench transistor 1′ having a large trench spacing, the avalanche breakdown takes place principally within the body region 6, which is indicated by the arrow denoted by reference numeral 11.
The object on which the invention is based is to specify a trench transistor by means of which it is possible to block leakage currents from an edge region of the trench transistor into the cell array, and at the same time it is possible to prevent a local lowering of the breakdown voltage in the edge region of the cell array, so that the provision of reserves becomes superfluous.